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DeMorgan’s Law, Decoder, MUX, Full Adder, and PLA!
In the previous blog, we looked at transistors and how to build logic gates from those transistors. In this blog, we are going to look at DeMorgan’s Law, the next level of abstraction, and the implementations and uses of those gates.
DeMorgan’s Law is a set of logical equivalencies. The laws govern the equivalence of AND/NAND/NOR/OR gates.
An example of DeMorgan’s Law would be the equivalence of NOT(NOT(A) AND NOT(B)). This would be equivalent to saying that “it is not true that A is false and B is false.” Well, if it is not the case that A is false and B is false, then that means it must be the case that A is true or B is true. Thus, the above logical statement is equivalent to A OR B.
For practice, try drawing this out in a truth table and see how the values compare.
Another example of DeMorgan’s Law would be the equivalence of NOT (A OR B). This would be equivalent to saying NOT A AND NOT B. Please see the truth table below for validation.
Now, we have seen in previous blogs how to build an AND gate, a NOR gate, an OR gate, and a NAND gate at the transistor level with two inputs, how do we expand these gates to accept three inputs or four inputs? Could we build such a gate with 8 inputs? As always, let’s look at an example!
